Designing a New Ternary Arithmetic Unit with Overflow ‎Detection Using Reversible Ternary

Mohammad Mehdi Panahi ‎

doi:10.14331/ijfps.2026.330185

Authors

Mohammad Mehdi Panahi ‎ Department of Computer Engineering, VaP.C., Islamic Azad University, Varamin, Iran ‎ Author

DOI:

https://doi.org/10.14331/ijfps.2026.330185

Keywords:

Quantum computing, reversible ternary logic, ternary parallel adder, reversible arithmetic unit, overflow detection

Abstract

Reversible ternary circuit design has attracted considerable attention because ternary logic can reduce interconnection ‎complexity relative to binary logic and is compatible with emerging quantum-computing and nanotechnology platforms. This ‎study proposes a reversible 2-trit ternary parallel adder with a quantum cost of 23, one constant input, and three garbage ‎outputs. Compared with previously reported counterparts, the proposed adder requires lower quantum cost and fewer ‎constant inputs and garbage outputs. Based on this adder, a reversible arithmetic unit is developed for two 2-trit unsigned ‎ternary numbers. The unit performs six arithmetic operations: A+B, A−B, A+1, A−1, A+B+1, and A−B−1. The unsigned inputs ‎and outputs are represented within the decimal range from 0 to 8. A reversible arithmetic unit for two signed 2-trit ternary ‎numbers is also proposed. This circuit has a quantum cost of 32 and requires only one constant input. It performs the same six ‎arithmetic operations using the 3’s-complement representation over the range from −4 to +4. In addition, a new reversible ‎overflow detection module is introduced for signed addition and subtraction. By integrating this module with the proposed ‎signed arithmetic unit, a complete reversible ternary arithmetic circuit with overflow-detection capability is obtained. All ‎proposed circuits are constructed using 1-qutrit shift gates and 2-qutrit Muthukrishnan–Stroud gates, which are primitive ‎ternary gates suitable for implementation in ion-trap quantum-computing technology.‎

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Author Biography

Mohammad Mehdi Panahi ‎, Department of Computer Engineering, VaP.C., Islamic Azad University, Varamin, Iran ‎

https://orcid.org/0000-0002-4730-8411

References

M. A. Nielsen and I. L. Chuang, Quantum Computation and Quantum Information. Cambridge University Press, Cambridge, 2000.

R. P. Feynman, “Quantum mechanical computers,” Foundations of Physics, vol. 16, pp. 507–531, 1986. DOI: https://doi.org/10.1007/BF01886518

A. Peres, “Reversible logic and quantum computers,” Physical Review A, vol. 32, pp. 3266–3276, 1985. DOI: https://doi.org/10.1103/PhysRevA.32.3266

N. Gershenfeld, “Signal entropy and the thermodynamics of computation,” IBM Systems Journal, vol. 35, pp. 577–586, 1996. DOI: https://doi.org/10.1147/sj.353.0577

V. V. Zhirnov, R. K. Cavin, J. A. Hutchby, and G. I. Bourianoff, “Limits to binary logic switch scaling—a Gedanken model,” Proceedings of the IEEE, vol. 91, no. 11, pp. 1934–1939, 2003. DOI: https://doi.org/10.1109/JPROC.2003.818324

R. Landauer, “Irreversibility and heat generation in the computing process,” IBM Journal of Research and Development, vol. 5, pp. 183–191, 1961. DOI: https://doi.org/10.1147/rd.53.0183

C. H. Bennett, “Logical reversibility of computation,” IBM Journal of Research and Development, vol. 17, pp. 525–532, 1973. DOI: https://doi.org/10.1147/rd.176.0525

A. P. Dhande, V. T. Ingole, and V. R. Ghiye, Ternary Digital System: Concepts and Applications. SM Online Publishers LLC, 2014.

D. M. Miller and M. A. Thornton, Multiple Valued Logic: Concepts and Representations. Morgan & Claypool Publishers, 2008. DOI: https://doi.org/10.2200/S00165ED1V01Y200810DCS001

M. H. A. Khan, “Quantum realization of multiple-valued Feynman and Toffoli gates without ancillary input,” in Proceedings of the 39th IEEE International Symposium on Multiple-Valued Logic, pp. 103–108, 2009. DOI: https://doi.org/10.1109/ISMVL.2009.31

M. H. A. Khan and M. Perkowski, “Quantum ternary parallel adder/subtractor with partially look-ahead carry,” Journal of Systems Architecture, vol. 53, pp. 453–464, 2007. DOI: https://doi.org/10.1016/j.sysarc.2006.11.003

A. T. Monfared and M. Haghparast, “Design of new quantum/reversible ternary subtractor circuits,” Journal of Circuits, Systems and Computers, vol. 25, no. 1, Art. no. 1650014, 2016. DOI: https://doi.org/10.1142/S021812661650014X

A. T. Monfared and M. Haghparast, “Designing new ternary reversible subtractor circuits,” Microprocessors and Microsystems, vol. 53, pp. 51–56, 2017. DOI: https://doi.org/10.1016/j.micpro.2017.07.001

M. Haghparast, R. Wille, and A. T. Monfared, “Towards quantum reversible ternary coded decimal adder,” Quantum Information Processing, vol. 16, no. 12, 2017. DOI: https://doi.org/10.1007/s11128-017-1742-1

M. M. Panahi, O. Hashemipour, and K. Navi, “A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates,” Integration, vol. 62, pp. 353–361, 2018. DOI: https://doi.org/10.1016/j.vlsi.2018.04.014

N. J. Lisa and H. M. H. Babu, “Design of a compact ternary parallel adder/subtractor circuit in quantum computing,” in Proceedings of the 45th IEEE International Symposium on Multiple-Valued Logic, pp. 193–198, 2015. DOI: https://doi.org/10.1109/ISMVL.2015.38

V. G. Deibuk and A. V. Biloshytskyi, “Design of a ternary reversible/quantum adder using a genetic algorithm,” International Journal of Information Technology and Computer Science, vol. 7, pp. 38–45, 2015.

V. Deibuk, “Reversible/quantum ternary arithmetic logic unit design,” International Journal of Innovative Computing, Information and Control, vol. 12, no. 3, pp. 827–838, 2016.

A. T. Monfared and M. Haghparast, “Design of novel quantum/reversible ternary adder circuits,” International Journal of Electronics Letters, vol. 5, no. 2, pp. 149–157, 2017. DOI: https://doi.org/10.1080/21681724.2016.1171912

M. H. A. Khan, M. A. Perkowski, M. R. Khan, and P. Kerntopf, “Ternary GFSOP minimization using Kronecker decision diagrams and their synthesis with quantum cascades,” Journal of Multiple-Valued Logic and Soft Computing, vol. 11, pp. 567–602, 2005.

M. M. Panahi, O. Hashemipour, and K. Navi, “A novel design of a multiplier using reversible ternary gates,” IETE Journal of Research, vol. 67, no. 3, pp. 349–358, 2021. DOI: https://doi.org/10.1080/03772063.2019.1567274

M. A. Asadi, M. Mosleh, and M. Haghparast, “An efficient design of reversible ternary full-adder/full-subtractor with low quantum cost,” Quantum Information Processing, vol. 19, no. 7, Art. no. 204, 2020. DOI: https://doi.org/10.1007/s11128-020-02707-4

M. A. Asadi, M. Mosleh, and M. Haghparast, “Toward novel designs of reversible ternary 6:2 compressor using efficient reversible ternary full-adders,” The Journal of Supercomputing, vol. 77, pp. 5176–5197, 2021. DOI: https://doi.org/10.1007/s11227-020-03485-7

A. Muthukrishnan and C. R. Stroud Jr., “Multivalued logic gates for quantum computation,” Physical Review A, vol. 62, Art. no. 052309, 2000. DOI: https://doi.org/10.1103/PhysRevA.62.052309

A. B. Klimov, R. Guzmán, J. C. Retamal, and C. Saavedra, “Qutrit quantum computer with trapped ions,” Physical Review A, vol. 67, Art. no. 062313, 2003. DOI: https://doi.org/10.1103/PhysRevA.67.062313

D. McHugh and J. Twamley, “Trapped-ion qutrit spin molecule quantum computer,” New Journal of Physics, vol. 7, Art. no. 174, 2005. DOI: https://doi.org/10.1088/1367-2630/7/1/174

J. Łukasiewicz, “O logice trójwartościowej (On three-valued logic),” Ruch Filozoficzny, vol. 5, pp. 169–171, 1920.